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SFI-4.1 16-Channel SDR Interface with Bus Alignment Summary

SerDes Framer Interface Level 4 Phase 2 Summary

Virtex-5 Gigabit Ethernet Serial Protocol Standard www.BDTIC.com/XILINX Characterization Test Report

SERDES Framer Interface Level 5 for Virtex-6 Devices Summary

High Performance Computing Using FPGAs

I/O and Memory Interfacing Features and Benefits in 7 Series Architecture

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics Introduction

CipherStream Protocol—How CoolRunner-II CPLDs Protect FPGA IP

SerDes Channel Simulation in FPGAs Using IBIS-AMI

High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design
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